`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/08/08 00:28:52
// Design Name: 
// Module Name: pcie_lite_map
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pcie_lite_map(
    input              bramctrl_clk,
	input              bramctrl_rst,
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input [13-1:0]     bramctrl_addr,
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input [31:0]       bramctrl_data_out,
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input [3:0]        bramctrl_we,
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input              bramctrl_en,
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) output[31:0]       bramctrl_data_in,
	//----------------------------------
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input      [31:0]                 seg_need_read,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input      [31:0]                 seg_need_write,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input      [31:0]                 seg_need_read_GNSS_PPS,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input      [31:0]                 seg_need_read_Delay_cnt,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) input      [31:0]                 PPS_control_back,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) output   reg  TX2Enable,
    (*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) output   reg  TX2Enable_TX,   //BY Z
	(*mark_debug = "FALSE"*)(* KEEP = "FALSE" *) output  reg   [31:0]  TestRegOut,	
	output  reg   [31:0] DAC_cnt_reset_val,
	output  reg   [31:0] LED_Val,
	input     [31:0]  TestRegIn	 
    );
    reg[31:0] seg_need_read_d1,seg_need_read_d2,seg_need_read_d3;

    always @(posedge bramctrl_clk)
    begin
        seg_need_read_d1<=seg_need_read;
        seg_need_read_d2<=seg_need_read_d1;
        seg_need_read_d3<=seg_need_read_d2;
    end
    reg[31:0] seg_need_write_d1,seg_need_write_d2,seg_need_write_d3;
    always @(posedge bramctrl_clk)
    begin
        seg_need_write_d1<=seg_need_write;
        seg_need_write_d2<=seg_need_write_d1;
        seg_need_write_d3<=seg_need_write_d2;
    end
    reg[31:0] seg_need_read_GNSS_PPS_d1,seg_need_read_GNSS_PPS_d2,seg_need_read_GNSS_PPS_d3;
    always @(posedge bramctrl_clk)
    begin
        seg_need_read_GNSS_PPS_d1<=seg_need_read_GNSS_PPS;
        seg_need_read_GNSS_PPS_d2<=seg_need_read_GNSS_PPS_d1;
        seg_need_read_GNSS_PPS_d3<=seg_need_read_GNSS_PPS_d2;
    end

    reg[31:0] seg_need_read_Delay_cnt_d1,seg_need_read_Delay_cnt_d2,seg_need_read_Delay_cnt_d3;
    always @(posedge bramctrl_clk)
    begin
        seg_need_read_Delay_cnt_d1<=seg_need_read_Delay_cnt;
        seg_need_read_Delay_cnt_d2<=seg_need_read_Delay_cnt_d1;
        seg_need_read_Delay_cnt_d3<=seg_need_read_Delay_cnt_d2;
    end
    
    reg[31:0] PPS_control_back_d1,PPS_control_back_d2,PPS_control_back_d3;
    always @(posedge bramctrl_clk)
    begin
        PPS_control_back_d1<=PPS_control_back;
        PPS_control_back_d2<=PPS_control_back_d1;
        PPS_control_back_d3<=PPS_control_back_d2;
    end
    
    always @(posedge bramctrl_clk)
    begin
        if(bramctrl_rst)begin
            LED_Val<=32'd0;
            TestRegOut<=32'd0;
            DAC_cnt_reset_val <= 32'd0;
        end
        else if((&bramctrl_we) & bramctrl_en) begin
 //       TestRegOut <= bramctrl_data_out;
            case(bramctrl_addr[11:0])
                12'h074: LED_Val <= bramctrl_data_out;
                12'h084: TestRegOut <= bramctrl_data_out;
                12'h094: DAC_cnt_reset_val <= bramctrl_data_out;
            default : ;
            endcase
        end
    end    
    //---------------------
    reg [31:0] bramctrl_rddata;
    always @(posedge bramctrl_clk)
    begin
        if(bramctrl_rst)
        begin
            bramctrl_rddata <= 0;
        end
        else if((bramctrl_we==4'b0)&bramctrl_en) begin
//        bramctrl_rddata<=TestRegIn;
//            bramctrl_rddata<= {20'd0 , bramctrl_addr[11:0]};
           case(bramctrl_addr[11:0])
                12'h050 : bramctrl_rddata <= seg_need_read_d3;	
                12'h054 : bramctrl_rddata <= seg_need_read_GNSS_PPS_d3;	
                12'h058 : bramctrl_rddata <= seg_need_write_d3; 
                12'h088 : bramctrl_rddata <= PPS_control_back_d3; 
                12'h098 : bramctrl_rddata <= seg_need_read_Delay_cnt_d3; 
               default : bramctrl_rddata <= bramctrl_rddata;
           endcase
        end
    end
    assign bramctrl_data_in = bramctrl_rddata;
    //-------------------generate  signal
    reg[32-1:0] ReadRegClkCnt;
    always @(posedge bramctrl_clk)
    begin
        if(bramctrl_rst)begin
            TX2Enable<=0;
            ReadRegClkCnt<=0;
        end
        else begin
            ReadRegClkCnt<=ReadRegClkCnt+1;
            if((bramctrl_we==4'b0)&bramctrl_en&&(bramctrl_addr[11:0] == 12'h054))begin
                ReadRegClkCnt<=0;
                TX2Enable<=1;
            end
            if(ReadRegClkCnt>32'd50000000)
                TX2Enable<=0;
        end
    end
    wire TestRecvReg;
    assign TestRecvReg = (bramctrl_we==4'b0)&bramctrl_en&&(bramctrl_addr[11:0] == 12'h054);
    
      //-------------------generate  signal fo tx 221018 by z
    reg[32-1:0] WeadRegClkCnt;
    always @(posedge bramctrl_clk)
    begin
        if(bramctrl_rst)begin
            TX2Enable_TX<=0;
            WeadRegClkCnt<=0;
        end
        else begin
            WeadRegClkCnt<=WeadRegClkCnt+1;
            if((bramctrl_we==4'b0)&bramctrl_en&&(bramctrl_addr[11:0] == 12'h058))begin
                WeadRegClkCnt<=0;
                TX2Enable_TX<=1;
            end
            if(WeadRegClkCnt>32'd40000000)  //by z
                TX2Enable_TX<=0;
        end
    end
    
    
    
    
    
endmodule
